Process for forming planarized, air-bridge interconnects on a se

Fishing – trapping – and vermin destroying

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437183, 437195, 437228, 148DIG20, 257750, H01L 21283

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active

051717131

ABSTRACT:
A process for fabricating a integrated circuit (IC), including a plurality of devices coupled together by a system of metal interconnects disposed above a semiconductor substrate comprises the steps of forming a plurality of conductive pedestals on the surface of the substrate. A portion of the pedestals form electrical contacts to the devices, wherein the height of the pedestals is higher than any feature of the substrate. After a polyimide layer is deposited on the substrate to a thickness which covers the pedestals, an etching step is performed until the top surface of the pedestals is coplanar with the polyimide layer. A set of metal interconnect lines is then formed over the polyimide and pedestals to form electrical connections to selected ones of the pedestal contacts.

REFERENCES:
patent: 3657029 (1972-04-01), Fuller
patent: 4614021 (1986-09-01), Hulseweh
patent: 4866008 (1989-09-01), Brighton et al.
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5018256 (1991-05-01), Hornbeck

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