Vertical DMOS transistor structure built in an N-well CMOS-based

Details Vertical DMOS transistor structure built in an N-well CMOS-based Vertical DMOS transistor structure built in an N-well CMOS-based

1990-10-03

1992-12-15

Quach, T. N.

Fishing, trapping, and vermin destroying

437 51, 437 57, 437 34, 437 31, H01L 21335

Patent

active

051716992

ABSTRACT:
An integrated circuit is provided wherein bipolar, CMOS and DMOS devices are merged together on one chip with fabrication taking place from a CMOS point of view rather than from a bipolar point of view as in the prior art and p-type epitaxial silicon is used as opposed to n-type epitaxial silicon in the prior art. The integrated circuit uses a P+ substrate upon which a P-epitaxial layer is formed. N+ buried regions isolate the DMOS, PMOS and NPN bipolar devices from the P-epitaxial layer. Each of the devices is formed in a N-well with a first level of polysilicon gate layer providing both the gate and masking for the backgate diffusion of the DMOS device and a sidewall oxide later formed on the first level gate layer to control the diffusion of the source and drain regions of the DMOS device to control channel length. A second level of polysilicon layer provides the gate structures for the CMOS devices as well as one plate of a capacitor. The second level of polysilicon acts as a mask for the source and drain region implants of the CMOS devices. A sidewall oxide later formed on the second polysilicon level further controls the channel lengths of the CMOS structures. A third level of polysilicon provides the second capacitor plate for the capacitor. The DMOS device is isolated from the remaining circuitry by the p-type epitaxial layer and the peripheral portion of the DMOS device is terminated by a PN junction.

REFERENCES:
patent: 4403395 (1983-09-01), Curran
patent: 4795716 (1989-01-01), Yilmaz et al.
patent: 4855244 (1989-08-01), Hutter et al.
patent: 4914051 (1990-04-01), Huie et al.

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