Counter using an inverter and shift registers

Details Counter using an inverter and shift registers Counter using an inverter and shift registers

1975-07-02

1977-04-26

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307221C, 307223C, H03K 2136, H03K 2308

Patent

active

040203620

ABSTRACT:
A counter comprises a cascade connection of an inverter stage and n one-bit shift register stages, the latter being operative in response to clock signals to be counted and each having a data-readin or front half-bit shift register stage and a data-readout or rear half-bit shift register stage. The output of the final stage in the cascade connection is coupled to the input of the first stage in the cascade connection. The output of the final stage is also coupled to an additional input of consecutive 1st to X-th shift register stages or consecutive 2nd to (X-1)-th shift register stages of an X-th shift register stage to constitute a scale-of-2n-X or 2n-(X-1) counter.

REFERENCES:
patent: 3421092 (1969-01-01), Bower et al.
patent: 3621402 (1971-11-01), Gardner
patent: 3745371 (1973-07-01), Suzuki
patent: 3766408 (1973-10-01), Suzuki et al.
patent: 3899691 (1975-08-01), Hama

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