Signal processor

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G06F 738

Patent

active

057038007

ABSTRACT:
An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.

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Stephan Olariu et al., "Time Optimal Sorting and Applications on nxn Enhanced Meshes", pp. 250-255 May 4, 1992.
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Nariankadu D. Hemkumar et al., "A Systolic VLSI Architecture for Complex SVD," pp. 1061-1064 May 10, 1992.
Christophe Joanblanq et al., "A 54-MHz CMOS Programmable Video Signal Processor for HDTV Applications", IEEE Journal of Solid-State Circuits, Jun., 1990, vol. 25, No. 3, pp. 730-734.

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