Method of making semiconductor device with PN junction in stacki

Details Method of making semiconductor device with PN junction in stacki Method of making semiconductor device with PN junction in stacki

1977-02-08

1978-09-26

Dean, R.

Metal treatment

Compositions

Heat treating

148191, 357 23, 357 88, H01L 752, H01L 1114

Patent

active

041167198

ABSTRACT:
In a method of making a semiconductor device, a semiconductor wafer having a stacking fault originally contained in the wafer or produced in the wafer through the thermal oxidation of the wafer surface is subjected to an annealing treatment in a non-oxidative atmosphere to eliminate the stacking fault. A PN junction is thereafter formed in an area of the wafer from which the stacking fault is eliminated.

REFERENCES:
patent: 3669768 (1972-06-01), Beadle et al.
patent: 3867196 (1975-02-01), Richman
patent: 3997368 (1976-12-01), Petroff et al.
G. A. Rozgonyi, et al., ". . . . Oxidation-Induced Stacking Fault by Preoxidation . . . . Si Wafers," J. Electr. Soc. 122, (1975), 1725.
Y. Sugita, et al., ". . . . Stacking Fault Generation in (111) Si Wafers," J. Electronics Mat. 4, (1975), 175.
H. Shiraki, "Si Wafer Annealing Effect in Loop Defect Generation," Jap. J. Appl. Phys. 13, (1974), p. 1514.
K. V. Ravi, "On the Annihilation of Oxidation Induced Stacking Faults in Si," Phil. Mag. 30, (1974), 1081.

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