Pattern recognition system using a four address arithmetic logic

Details Pattern recognition system using a four address arithmetic logic Pattern recognition system using a four address arithmetic logic

1994-10-07

1998-02-10

Ellis, Richard

395384, G06F 9302

Patent

active

057179085

ABSTRACT:
An instruction execution unit having an instruction format with four addresses. Two of the addresses may be defined as sources for operands. Two of the four addresses may be defined as a destination for the result of the computational unit and a pointer updated by a pointer pipeline. There are two arithmetic pipelines, and two pointer pipelines that operate in parallel to perform computations indicated by specially developed instruction format. The pipelines are specially optimized for Hidden Markov Models and Dynamic Time Warping procedures used for pattern recognition. The available addresses that can be used as two sources of operands are not symmetrical. Therefore, the instruction set is implemented such that operations are defined in pairs with counterpart operations using reciprocal operands to add full flexibility to the arithmetic pipeline. Using four address instruction format with a specialized type field, the present invention is able to develop a fully flexible addressing scheme offering up to 27 different addressing combinations for each instruction format. Further, computations within an arithmetic pipeline may be performed utilizing source data in byte or word format within any degradation in processing efficiency.

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