Selectively operable cache memory

Details Selectively operable cache memory Selectively operable cache memory

1997-05-06

1998-02-10

Chan, Eddie P.

395403, 395405, 39542103, 395438, 395464, 395494, G06F 1200

Patent

active

057178925

ABSTRACT:
A cache memory in which the address of a required data item is compared with address data stored in a plurality of tag memory sections, a match indicating that the required data item is stored in a corresponding data memory section, is operable in at least a first and a second mode, whereby:
(i) in the first mode, only that one of the data memory sections in which the required data word is stored is enabled for operation once the appropriate data memory section has been identified by an address match with the corresponding tag memory section; and
(ii) in the second mode, two or more (and preferably all) of the data memory sections are enabled for operation substantially concurrently with the comparison of the required address and the addresses stored in the tag memory sections, an address match being used to select the output of one of the data memory sections.

REFERENCES:
patent: 4317181 (1982-02-01), Teza et al.
patent: 4862348 (1989-08-01), Nakamura
patent: 5018061 (1991-05-01), Kishigami et al.
patent: 5083266 (1992-01-01), Watanabe
patent: 5519667 (1996-05-01), Harston

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