Method and apparatus for the error-free synchronization of async

Details Method and apparatus for the error-free synchronization of async Method and apparatus for the error-free synchronization of async

1982-02-11

1985-02-05

Smith, Jerry

Excavating

307269, 307480, H03K 3295, H03K 513

Patent

active

044981767

ABSTRACT:
Method and apparatus for the error-free synchronization of asynchronous pulses through logical interconnection of the asynchronous pulses with clock pulses of constant frequency by means of a flip-flop, which includes comparing output voltages of the flip-flop with a predetermined threshold voltage for determining a metastable state of the flip-flop, and flipping the flip-flop into a third stable state until the next clock pulse appears if a metastable state is present, for preventing an evaluation of the output voltages of the flip-flop.

REFERENCES:
patent: 3947697 (1976-03-01), Archer
patent: 3953744 (1976-04-01), Kawagoe
patent: 4093878 (1978-06-01), Paschal et al.
patent: 4128201 (1978-12-01), Barron et al.
Halbleiter-Schaltungstechnik, 1980, p. 514.
Introduction to VLSI-Systems, 1980, pp. 236-242.
IEEE Transactions on Computers, Feb. 1976, pp. 133-139.

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