System for polynomial division self-testing of digital networks

Details System for polynomial division self-testing of digital networks System for polynomial division self-testing of digital networks

1982-07-26

1985-02-05

Atkinson, Charles E.

Excavating

371 15, G01R 3128

Patent

active

044981724

ABSTRACT:
A built-in test system employs dual-mode feedback shift registers to supply test vectors and evaluate test responses of functional and interface networks of a logic system. Test responses are supplied to a quotient bit compressor which generates a system response signature for comparison with an expected fault-free signature to produce a system pass/fail status signal.

REFERENCES:
patent: 3739160 (1973-06-01), El-Hasan et al.
patent: 4433413 (1984-02-01), Fasang
Benowitz, Norman, "Fault Detection/Isolation Results from AAFIS Hardware Built-In Test", NAECON '76 Record, pp. 215-222.
Frohwerk, Robert A., "Signature Analysis: A New Digital Field Service Method", Hewlett-Packard Journal, May 1977, pp. 2-8.
Konemann, Bernd, et al., "Built-In Logic Block Observation Techniques", Proceedings 1979 IEEE Test Conference, pp. 37-41.
Bhavsar, Dilip K., et al., "Self-Testing by Polynomial Division", Digest of Papers 1981 International Test Conference, IEEE, pp. 208-216.

Affiliated with

Also associated with

Rating

System for polynomial division self-testing of digital networks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for polynomial division self-testing of digital networks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for polynomial division self-testing of digital networks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2085590