Improved-accuracy fast-Fourier-transform butterfly circuit

Details Improved-accuracy fast-Fourier-transform butterfly circuit Improved-accuracy fast-Fourier-transform butterfly circuit

1995-10-24

1998-02-10

Malzahn, David H.

Boots, shoes, and leggings

G06F 1714

Patent

active

057176205

ABSTRACT:
A channelizer (16) and combiner (22) in a cellular-telephone base station (10) are implemented in fast-Fourier-transform butterfly circuits (FIG. 4 ) in which outputs of adders (40, 46) are applied to successive adders (46, 50) in bit alignment. Although this makes it necessary for the input to the first adder (40) to leave some of the adder's input-port bit width unused in order to avoid the carries that a bit-aligned architecture cannot accommodate, the resultant accuracy exceeds that of a bit-offset architecture, because it can take advantage of rounding (56, 58) applied to each fast-Fourier-transform pass's input operands.

REFERENCES:
patent: 4996661 (1991-02-01), Cox et al.
patent: 5313413 (1994-05-01), Bhatia et al.
patent: 5343208 (1994-08-01), Chesley
patent: 5481488 (1996-01-01), Luo et al.
"PDSP16510A Stand Alone FFT Processor," GEC Plessey, pp. 200-220.
"PDSP16515A Stand Alone FFT Processor," GEC Plessey, Aug. 1994, pp. 1-23.

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