Parallel digital computer architecture

Details Parallel digital computer architecture Parallel digital computer architecture

1981-09-21

1982-09-21

Thomas, James D.

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364133, G06F 916

Patent

active

043510256

ABSTRACT:
A parallel digital computer with which real-time simulations can be performed. A multiplicity of elemental computers are joined in a parallel architecture through a master computer and shared memory system. Real-time operation of the elemental computers and master computer are time interleaved without overlap. Input data entering each elemental computer is processed according to the designated function during one time segment, succeeded by a master computer operating time segment during which the resultant elemental computer data is selectively transferred to the appropriate elemental computers for the next processing sequence. A real-time clock synchronizes the alternating time segments, allocating sufficient time for the processing performed by the elemental computer and the subsequent data transfer steps. Integration, unlike addition, subtraction and the numerous other arithmetic and logic functions, is performed only once per frame time. To maintain simulation accuracy, the frame time is defined to be short in comparison to the period of the highest frequency present in the real-time simulation. On the other hand, the frame time must be sufficiently long to satisfy the time demands of the intra-frame time cycling between elemental and master computers which is bounded by the elemental computer processing rate and the number of non-integrator elemental computer functions between successive elemental computers operating as integrators.

REFERENCES:
patent: 3349375 (1967-10-01), Seeber et al.
patent: 3363234 (1968-01-01), Erickson et al.
patent: 3533076 (1970-10-01), Perkins et al.
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4104720 (1978-08-01), Gruner
patent: 4128880 (1978-12-01), Gray, Jr.

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