Programmable frequency divider

Details Programmable frequency divider Programmable frequency divider

1980-02-05

1982-05-25

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307224R, H03K 2136

Patent

active

043319262

ABSTRACT:
A programmable frequency divider includes a programmable counter which comprises flip-flops 1 to 11 of a number less by one than the number of bits in a program value. The divider has first and second control circuits 101, 102 which respectively control every half period of a preset divided output pulse alternately, the second control circuit acting to delay the moment of the control in response to the least significant bit having a selected logic level, thereby enabling one to reduce the clock pulse frequency to a half in comparison with a conventional one. One can also obtain an optional sub-output signal of twice or one-half the frequency of a preset frequency output signal. Refer to FIG. 2.

REFERENCES:
patent: 3967205 (1976-06-01), Rossi et al
patent: 3976946 (1976-08-01), Schroder
patent: 3992635 (1976-11-01), Suzuki et al.

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