Complementary MOS logic decoder circuit

Details Complementary MOS logic decoder circuit Complementary MOS logic decoder circuit

1979-11-01

1982-09-21

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 340347DD, H03K 19094, H03K 19173, H03K 1920, H03K 1300

Patent

active

043509053

ABSTRACT:
A logic circuit having a first logic means for producing a first logic output signal having a plurality of MOS transistors of a first channel type, a second logic means for producing a second logic output having a plurality of MOS transistors of the first channel type, a first MOS transistor of a second channel type connected to the output terminal of the first logic output, and a second MOS transistor of the second channel type connected to the output terminal of said second logic output. In the logic circuit, the output terminal for the first logic output signal is coupled with the gate of the second MOS transistor. The output terminal for the second logic output is connected to the gate of the first MOS transistor.

REFERENCES:
patent: 3613055 (1971-10-01), Varadi et al.
patent: 3651342 (1972-03-01), Dingwall
patent: 3679911 (1972-07-01), Kaufman
patent: 3825772 (1974-07-01), Ainsworth
patent: 3938109 (1976-02-01), Gionis et al.
patent: 4063118 (1977-12-01), Nishimura
patent: 4124900 (1978-11-01), Smith et al.
patent: 4189782 (1980-02-01), Dingwall
Craig et al., "Cross-coupled FET Driver Circuit;" IBM Tech. Discl. Bull.; vol. 17, No. 12, pp. 3538; 5/1975.
RCA Solid State "COS/MOS Integrated Circuit;" SSD250, 1977, p. 114, CD 4028B Type COS/MOS BCD to Decimal Decoder.

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