Method of fabricating narrow deep grooves in silicon

Details Method of fabricating narrow deep grooves in silicon Method of fabricating narrow deep grooves in silicon

1980-11-04

1982-05-25

Kendall, Ralph S.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 94, 156643, 156657, 1566591, H01L 2176

Patent

active

043317081

ABSTRACT:
A method of fabricating deep grooves having submicron widths in a semiconductor substrate. A pattern of submicron oxidation masking elements formed on the substrate surface serves as an oxidation mask for a thick oxide layer. After forming the oxide layer, the insulating elements are removed to form a pattern of submicron width openings in the oxide extending to the substrate. A selective anisotropic dry etch is then used to form deep, narrow grooves in the substrate conforming to the pattern of openings which are filled with an insulating material formed by thermal oxidation, chemical vapor deposition, or a combination thereof. This process is used to provide deep dielectric isolation between active areas in high density integrated circuits.

REFERENCES:
patent: 4001465 (1977-01-01), Graul et al.
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4172005 (1979-10-01), Muraoka et al.

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