Pulse or digital communications – Synchronizers
Patent
1997-11-28
2000-06-13
Chin, Stephen
Pulse or digital communications
Synchronizers
375220, 375370, 375372, 710 31, 710 61, 710106, 710129, 710130, 713400, 713401, H04L 700, G06F 1300, G06F 1314, G06F 1328
Patent
active
060758309
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an arrangement by which a circuit provided with an asynchronous bus can be adapted to peripheral interface circuits that require a synchronous bus.
2. Description of the Related Art
Many digital processors have an asynchronous bus which is controlled by two timing control signals. An asynchronous bus may cause difficulties in applications that are strict as far as timing is concerned. The libraries of some producers of Application Specific Integrated Circuits (from hereafter "ASIC circuits") also contain synchronous memories only, or using such a memory instead of an asynchronous memory is otherwise feasible. In order to adapt a synchronous memory to an asynchronous bus, interface logic is required.
In many digital processors, such as the AT&T.RTM. signal processor DSP1610, the bus is controlled by two timing control signals. In the figures, they are presented as signals ENA' and RWN. State 0 of the signal ENA' (Enable) indicates that the processor carries out either a read or a write transaction. State 0 of the signal RWN (Read/Write-Not) indicates that the processor is writing to peripheral circuits, and state 1 of the same signal indicates that the processor is reading from the peripheral circuits. If ENA' is "1", the state of the signal RWN' is of no importance.
Formerly, digital processors have been coupled to ASIC circuits by applying both of the control signals ENA' and RWN to peripheral circuits. This results in certain drawbacks. First of all, some circuits only have one line to which a timing control signal can be coupled. In addition, the fact that the transitions of the signals ENA' and RWN have not necessarily been synchronized to the system clock (CKO) may cause problems in applications that are critical as far as timing is concerned. Furthermore, some ASIC circuit suppliers only have synchronous memories to offer, which means that it is not possible to employ all existing peripheral interface circuits on an asynchronous bus. In addition, an environment requiring two control signals for timing is rather poorly, or not at all, supported by development tools. Test generation is also facilitated if timing takes place with one control signal.
SUMMARY OF THE INVENTION
The object of the present invention is to obtain methods and arrangements for eliminating the problems and limitations described above. This object is achieved with the methods according to claims 1 and 2, and circuit arrangements according to claims 3 and 4.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following, the invention will be described in closer detail by means of drawings, in which:
FIG. 1 is a block diagram illustration of adapting interfaces according to the invention.
FIG. 2 illustrates an adapting interface of the invention for transferring data from an asynchronous circuit to a synchronous circuit.
FIG. 3 shows an impulse diagram in a circuit corresponding to FIG. 2.
FIG. 4 illustrates an adapting interface of the invention for transferring data from a synchronous circuit to an-asynchronous circuit.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
The positioning of the adapting interfaces of the invention are shown in FIG. 1. Between an asynchronous circuit 1 and a synchronous circuit 2 there is arranged an adapting interface 3, which carries out the transfer of data (DATA) from the asynchronous circuit 1 to the synchronous circuit 2, and an adapting interface 4 which carries out the transfer of data in the reverse direction. According to requirements at any one time, one or both adapting interfaces 3 and 4 of the invention can be used.
In the following, the operation of the adapting interface 3 of the invention is examined on the basis of FIG. 2 and the associated pulse diagram 3. The figures present the blocks that are essential to the invention: the asynchronous circuit 1 (e.g. a digital signal processor), the synchronous circuit 2 and the adapting interface 3 in accordance with the invention. In the pulse diagram 3, it is ass
REFERENCES:
patent: 4935942 (1990-06-01), Hwang et al.
patent: 5070443 (1991-12-01), Priem et al.
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5357613 (1994-10-01), Cantrell et al.
patent: 5524270 (1996-06-01), Haess et al.
patent: 5673398 (1997-09-01), Takeda
patent: 5684841 (1997-11-01), Chiba et al.
patent: 5758188 (1998-05-01), Appelbaum et al.
Chin Stephen
Maddox Michael W.
Nokia Telecommunications Oy
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