Method for sorting semiconductor devices having a plurality of n

Details Method for sorting semiconductor devices having a plurality of n Method for sorting semiconductor devices having a plurality of n

1999-02-22

2000-06-13

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

365201, 36518509, G11C 1604

Patent

active

060757248

ABSTRACT:
A method for sorting semiconductor devices having a plurality of non-volatile memory cells effectively screens memory cells with a predicted lifetime less than a desired lifetime, in part, by determining a minimum acceptable voltage value and a maximum acceptable voltage drop value for each cell in the device at a margin sort read point. In the method of the invention, the device is first stressed by programming and erasing the memory cells for a predetermined number of cycles. After stressing the device, the device is erased and an initial voltage across a floating-gate is measured at time=0. The initial voltage value is compared with acceptable minimum and maximum initial voltages. The device is discarded if the initial voltage value is outside of the range defined by the minimum and maximum initial voltages. Next, the device is baked at a predetermined temperature. Then, a voltage drop value is determined by measuring a second voltage on the floating-gate at the margin sort read point. The device is identified as defective and discarded if both the second voltage value of any cell is below the predetermined minimum value, and if the voltage drop value of the cell exceeds a predetermined maximum voltage drop value.

REFERENCES:
patent: 4963825 (1990-10-01), Mielke
patent: 5687120 (1997-11-01), Chang et al.
patent: 5700698 (1997-12-01), Barsan et al.

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