ESD protection circuit for mixed mode integrated circuits with s

Details ESD protection circuit for mixed mode integrated circuits with s ESD protection circuit for mixed mode integrated circuits with s

1997-07-09

2000-06-13

Leja, Ronald W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

H02H 900

Patent

active

060756861

ABSTRACT:
An ESD protected circuit is provided for protecting first and second internal circuits against ESD failure. The first and second internal circuits are respectively connected to either a first or a second power supply bus. The first and second power supply busses are mutually isolated from each other and are of the same polarity. The ESD protected circuit includes a first ESD protection circuit connected to the first power supply bus. A second ESD protection circuit is also provided which is connected to the second power supply bus. A third ESD protection circuit is connected between the first and second power supply busses. The third ESD protection circuit is for selectively connecting the first and second power supply busses only during an ESD event so that ESD energy applied to one of the first or second power supply busses couples to a second one of the first or second power supply busses. ESD energy coupled between the first and second power supply busses is also coupled through at least one of the first or second ESD protection circuits to ground.

REFERENCES:
patent: 4855863 (1989-08-01), Yoshitake
patent: 5530612 (1996-06-01), Maloney
patent: 6002568 (1999-12-01), Ker et al.
patent: 6011681 (2000-01-01), Ker et al.

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