Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Identifying or correcting improper counter operation
Patent
1997-06-19
2000-11-14
Callahan, Timothy P.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Identifying or correcting improper counter operation
377 47, 327 48, G06M 300
Patent
active
06148055&
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a counting apparatus which can output counting results while monitoring for whether or not a counting operation is being carried out normally. Moreover the invention relates to a counting apparatus which verifies that the apparatus has been reset to an initial condition, before beginning the counting operation. Furthermore, the present invention relates to a rotation stopped detection apparatus which uses a counting apparatus to detect, in a fail-safe manner, if a rotation body has stopped rotating.
BACKGROUND ART
Heretofore, as a counting apparatus which carries out a counting operation while monitoring for whether or not the counting operation is being carried out normally, there is for example a device as disclosed in Japanese Examined Patent Publication No. 4-41532, which is utilized in a time element circuit.
In this time element circuit, there is provided two oscillators having different oscillation frequencies, the arrangement being such that when an input voltage is lost, a high frequency oscillation output from one of the oscillators is input to a counter. When the high frequency oscillation output reaches a predetermined number the counter is set, and due to the output from the counter, a delay output from after the loss of the input voltage is self held. Then due to the self held output, a low frequency oscillation output from the other oscillator is input to the counter. Subsequently, when the low frequency oscillation output attains a predetermined number, the counter is reset and the output from the self hold circuit is stopped. More specifically, the construction is such that the number of inputs of low frequency oscillation outputs is counted from after the high frequency oscillation output has reached a predetermined number, to thereby obtain the delay time. By using a counting apparatus in this way, the precision of the time element circuit is increased.
However, with the above described conventional counting apparatus applied to a time element circuit, monitoring for whether or not the counter is operating normally is carried out before counting the low frequency oscillation output, at the point in time of starting the counting operation for the low frequency oscillation output. This is done by making the counter carry out a high speed counting operation using the high frequency oscillation output. That is to say, with the conventional counting apparatus, the construction is such that monitoring of the operation of the counter is carried out before the counting operation for the input signal of the signal being counted.
In practice however, whether or not the counter is operating normally, should be ascertained after completion of the counting operation for the input signal of the signal being counted, so that the latest operating condition for the counter is monitored.
Moreover, the above described counter is generally an electronic circuit comprising a plurality of frequency dividers connected in cascade. For this to be a so called fail-safe counter where an input pulse signal of the signal being counted is counted and an output is not produced until this reaches a predetermined number, while at the time of a fault, the generation of an output is never premature, then for the counter to fulfill the important role in a control where safety is of concern, the abovementioned fail-safe counter performance is required.
Conventional counters however do not necessarily satisfy the abovementioned fail-safe counter performance.
For example, a counter may be considered wherein n frequency dividing circuits made up of flip-flop circuits (referred to hereunder as F.cndot.F circuits) are connected in cascade. Here if the signal being counted is a clock signal, then the counting operation is carried out using, for example, the falling of the clock signal.
In this case the frequency dividing circuits are reset when a reset signal of an L level is input to an active low reset terminal, and the counting operation is started when the reset signal rise
REFERENCES:
patent: 4189635 (1980-02-01), Sheller
patent: 4881248 (1989-11-01), Korechika
patent: 5127035 (1992-06-01), Ishii
Futsuhara Koichi
Sakai Masayoshi
Callahan Timothy P.
Nguyen Minh
The Nippon Signal Co. Ltd.
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