System for generating a plurality of different addresses for a w

Details System for generating a plurality of different addresses for a w System for generating a plurality of different addresses for a w

1980-03-26

1982-07-13

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 922

Patent

active

043397964

ABSTRACT:
A system is disclosed for a microcontroller which permits the interruption of a sequence of instructions, each of which are executable in a fixed machine cycle in response to one of a plurality of interrupt/trap signals. The microcontroller is interrupted for one fixed period machine cycle, during which period one of a plurality of instructions are read out from an instruction storage location of a memory determined by the active interrupt/trap signal concurrently as data stored in separate registers, which define the condition of the microcontroller at the point of interruption, are transferred to one group of locations in a storage device which is different than the memory which stores the instruction. After the transfer, another group of storage locations also determined by the active trap request signal is available to instructions which executed in subsequent machine cycles. The system further responds to a set machine level instruction of the microcontroller which functions to transfer the data defining the previous condition of the microcontroller at the point of interruption which has been stored in the storage device back to the plurality of registers. The system allows the microprogrammer a choice between treating the interrupt/trap signal as either a true interrupt to the program, which must be continued from the point of interruption, or a fast trap in the program where there is a need to take some immediate action and, in certain circumstances, no need or desire to return to the point of interruption.

REFERENCES:
patent: 4074353 (1978-02-01), Woods et al.

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