MX bus translation to new system bus protocol

Details MX bus translation to new system bus protocol MX bus translation to new system bus protocol

1996-11-14

1999-02-16

An, Meng-Ai T.

395280, 395284, 395306, 395307, 395308, 395309, 395310, G06F 1300

Patent

active

058729453

ABSTRACT:
A bus translator is provided to translate the internal bus structure of a self-contained processor system to a system bus which is easily compatible with a plurality of different external components. In particular, the bus translator translates the packetized multiplexed internal bus to a de-multiplexed bus. The translator further provides the ability to add wait states to the transactions in order to accommodate slower memories and devices coupled to the system bus. Furthermore, the translator accommodates bus burst logic by providing an auto-increment addressing capability. In addition, as the processor operates on 32-bit words and coupled devices may operate on a smaller word size, the bus translator of the present invention provides a byte enable register file for performing byte operations within the 32-bit word operations of the system. Finally, the bus translator also provides accurate parity generation and checking on a byte basis. An external boot feature for the self-contained processor system allows the reading of start-up configuration data from internal non-volatile memory or system memory. Furthermore, address mapping and chip enable control allow the user to access additional information from the non-volatile memory regardless of the boot mode chosen.

REFERENCES:
patent: 4802119 (1989-01-01), Heene et al.
patent: 4827408 (1989-05-01), Shimomura
patent: 5228134 (1993-07-01), MacWilliams et al.
patent: 5276839 (1994-01-01), Robb et al.
patent: 5317711 (1994-05-01), Bourekas et al.
patent: 5349565 (1994-09-01), Wu et al.
patent: 5379384 (1995-01-01), Solomon
patent: 5388215 (1995-02-01), Baker et al.
patent: 5390356 (1995-02-01), Houlberg
patent: 5446849 (1995-08-01), Minagawa et al.
patent: 5467295 (1995-11-01), Young et al.
patent: 5473770 (1995-12-01), Vrba
patent: 5546391 (1996-08-01), Hochschild et al.
patent: 5590349 (1996-12-01), Robinson et al.
patent: 5617553 (1997-04-01), Minagawa et al.
patent: 5659748 (1997-08-01), Kennedy
patent: 5684980 (1997-11-01), Casselman

Affiliated with

Also associated with

Rating

MX bus translation to new system bus protocol does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MX bus translation to new system bus protocol, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MX bus translation to new system bus protocol will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2070110