IC with isolated analog signal path for testing

Details IC with isolated analog signal path for testing IC with isolated analog signal path for testing

1997-01-16

1999-02-16

DeCady, Albert

Excavating

371 2231, H04B 1700

Patent

active

058729089

ABSTRACT:
In an integrated circuit that includes a signal path for carrying an analog signal, a test voltage from a test voltage node (V+) is applied (S2, S3) to the signal path, and the test voltage is maintained (AOA, VME) on the signal path independently of the test voltage node.

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Nai-Chi Lee, "A Hierarchical Analog Test Bus Framework for Testing Mixed-Signal Integrated Circuits and Printed Circuit Boards", Journal of Electronic Testing, vol. 4, No. 4, 1 Nov. 1993,pp. 361-368.
Wilkins B R et al, "A Structure for Interconnect Testing on Mixed-Signal Boards", Journal of Electronic Testing, vol. 4, No. 4, 1 Nov. 1993, pp. 369-374.
Thatcher C W et al, "Towards a Test Standard for Board and System Level Mixed-Signal Interconnects", Proceedings of the International Test Conference, Baltimore, Oct. 17-21, 1993; 1 Jan. 1993, pp. 300-308.
Kenneth P. Parker, John E. McDerid and Stig Oresjo, "Structure and Metrology for an Analog Testability Bus", International Test Conference 1993, paper 15.2 pp. 309-317.
Bharsar, Chapter 17: Cell Designs That Help Test Interconnect Shorts, 1990 IEEE, pp. 183-189.

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