High-performance computer system of a parallel write-buffering t

Details High-performance computer system of a parallel write-buffering t High-performance computer system of a parallel write-buffering t

1997-02-07

1998-04-21

Kim, Matthew M.

395432, 395494, 395469, 395410, G06F 1300

Patent

active

057428492

ABSTRACT:
A computer system including a high speed CPU, a low speed main memory, and a system controller which has a write buffer coupled to the processor data bus in parallel to the main memory for latching CPU write data. The system controller includes a gate array LSI, and an address buffer which is coupled to the CPU through a processor address bus and to the main memory through a memory address bus. When the write buffer latches the write data from the CPU, the system controller suspends the transfer of the write data to the main memory before completion of the memory write cycle. The memory write cycle is completed by transferring the latched data in the write buffer to the main memory before the CPU begins the next read/write cycle. This above configuration enables the CPU to operate with increased performance during read/write cycles and since the write buffer is connected to the CPU and main memory in parallel the number of pins required for interfacing the write buffer to the CPU and main memory is reduced compared to a configuration using a serially connected write buffer.

REFERENCES:
patent: 4157587 (1979-06-01), Joyce et al.
patent: 4621320 (1986-11-01), Holste et al.
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4727491 (1988-02-01), Culley
patent: 5034917 (1991-07-01), Bland et al.
patent: 5117493 (1992-05-01), Jensen
patent: 5263142 (1993-11-01), Watkins et al.
patent: 5276849 (1994-01-01), Patel
patent: 5285323 (1994-02-01), Hetherington et al.
patent: 5289584 (1994-02-01), Thome et al.
patent: 5355348 (1994-10-01), Ooishi
patent: 5388242 (1995-02-01), Jewett
patent: 5430844 (1995-07-01), Shitara et al.
patent: 5452463 (1995-09-01), Parks et al.
patent: 5459842 (1995-10-01), Begun et al.
patent: 5526505 (1996-06-01), Ludwig
patent: 5526507 (1996-06-01), Hill
patent: 5561783 (1996-10-01), Vanka et al.
Margulis, Build a Multibus II single-board computer, Electronics Design, vol. 37, No. 22, p. 79(6), Oct. 26, 1989.

Affiliated with

Also associated with

Rating

High-performance computer system of a parallel write-buffering t does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High-performance computer system of a parallel write-buffering t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-performance computer system of a parallel write-buffering t will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2068735