Parity generation and check circuit and method in read data path

Details Parity generation and check circuit and method in read data path Parity generation and check circuit and method in read data path

1996-05-03

1999-02-16

Tu, Trinh L.

Excavating

371 211, 365201, 39518505, G06F 1100

Patent

active

058728023

ABSTRACT:
The present invention provides a circuit and method for generating a parity bit and checking the parity of data words positioned in the read data path of a memory device or buffer. The parity check mode can detect errors. The parity generation mode generates EVEN or ODD parity as an additional bit. Other devices in the system may generally be configured to accept either EVEN or ODD parity. The parity generation and checking circuit can detect errors in both the data input to the buffer as well as errors created in the storage of the data by the buffer.

REFERENCES:
patent: 4604727 (1986-08-01), Shah
patent: 4802122 (1989-01-01), Auvinen et al.
patent: 4839866 (1989-06-01), Ward et al.
patent: 4875196 (1989-10-01), Spaderna et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 4901320 (1990-02-01), Sawada et al.
patent: 5084837 (1992-01-01), Matsumoto et al.
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5228002 (1993-07-01), Huang
patent: 5262996 (1993-11-01), Shiue
patent: 5305253 (1994-04-01), Ward
patent: 5311475 (1994-05-01), Huang
patent: 5317756 (1994-05-01), Komatsu et al.
patent: 5349683 (1994-09-01), Wu et al.
patent: 5367486 (1994-11-01), Mori et al.
patent: 5404332 (1995-04-01), Sato et al.
patent: 5406273 (1995-04-01), Nishida et al.
patent: 5406554 (1995-04-01), Parry
patent: 5424989 (1995-06-01), Hagiwara et al.
patent: 5426612 (1995-06-01), Ichige et al.
patent: 5428575 (1995-06-01), Fudeyasu
patent: 5450424 (1995-09-01), Okugaki et al.
patent: 5467319 (1995-11-01), Nusinov et al.
patent: 5469450 (1995-11-01), Cho
patent: 5490257 (1996-02-01), Hoberman et al.
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 5513318 (1996-04-01), van de Goor et al.
patent: 5521876 (1996-05-01), Hattori et al.
patent: 5546347 (1996-08-01), Ko et al.

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