Simulation apparatus and simulation method for semiconductor int

Details Simulation apparatus and simulation method for semiconductor int Simulation apparatus and simulation method for semiconductor int

1996-08-09

1999-02-16

Trans, Vincent N.

Boots, shoes, and leggings

364489, G06F 1750

Patent

active

058727248

ABSTRACT:
A simulation apparatus for a semiconductor integrated circuit is provided that includes model preparing device, logic simulating device and power supply voltage drop simulating device. The model preparing device prepares a feeder system model including current sources that correspond to respective circuit elements constituting a circuit to be designed, and power supply wiring and ground wiring for applying voltage to the current sources, on the basis of a result of automatic layout of the circuit. The logic simulating device implements logic simulation of the circuit, and outputs event information related to the circuit elements which have undergone a change of a condition thereof. The power supply voltage drop simulating device implements simulation while driving the current sources in the feeder system model that correspond to the circuit elements listed in the event information, and computing voltage drop in the power supply wiring and the ground wiring.

REFERENCES:
patent: 5051938 (1991-09-01), Hyduke
patent: 5305229 (1994-04-01), Dhar
patent: 5446676 (1995-08-01), Huang et al.
patent: 5461575 (1995-10-01), Schucker et al.
patent: 5553008 (1996-09-01), Huang et al.
Lee et al., "EDLICS: A New Relaxation-Based Electrical Circuit Simulation Technique", IEEE, 1994, pp. 1-4.
Sarin et al., "A Power Modeling and Characterization Method for Logic Simulation", IEEE, 1995, pp. 16.1.1-16.1.4.

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