Programmable test point selector circuit

Registers – Systems controlled by data bearing records – Time analysis

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Details

324 73R, G06F 1104, G01R 3100

Patent

active

041802039

ABSTRACT:
A programmable test point selector circuit for interfacing a test set with a system to be tested is disclosed. Typically, the system to be tested is provided with a multi-pin connector or receptacle to which the automatic test set is connected. The disclosed programmable test point selector circuit is interposed between the test set and this connector. Digital program words from the test set are used to designate pins of the multi-pin connector for use as either an input pin or an output pin. Additionally, the programmable test point selector permits at least one voltage level of the digital signal supplied to any pin designated as an input to be independently programmed over a wide range of values. An output sensing circuit is also provided which permits any individual pin or group of pins to be selected for monitoring to determine the voltage level of the signal present at the selected output pin relative to a threshold level. The threshold level of the output sensing circuit is also programmable so that each output pin of the device being tested may be monitored for the correct level. Thus, the device under test can have a mixture of voltage levels on its output pins. The program to the programmable test point selector circuit is a series of digital signals supplied by the associated test system.

REFERENCES:
patent: 3764995 (1973-10-01), Helf, Jr. et al.
patent: 3772595 (1973-11-01), DeWolf et al.
patent: 3849726 (1974-11-01), Justice
patent: 3892954 (1975-07-01), Neuner
patent: 3927371 (1975-12-01), Pomeranz et al.

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