Boots – shoes – and leggings
Patent
1996-08-02
1999-02-16
Teska, Kevin J.
Boots, shoes, and leggings
364490, G06F 1750
Patent
active
058727191
ABSTRACT:
In designing wiring for semiconductor integrated circuits, wiring channels are assigned to reduce a signal delay time developed parallel traces. The selection of the wiring channels for all of the wiring oriented nets of the circuits is based on the trunk trace length between the terminals. For the longer trunk trace lengths, a double-pitch wiring channel is assigned. First, the determined trunk-trace lengths are sorted in decreasing order of length. Then, a double-pitch wiring channel is assigned for the trunk-trace lengths that are greater than a predetermined length. When no double pitch channels remain, single pitch channels are used.
REFERENCES:
patent: 3621208 (1971-11-01), Isett et al.
patent: 3644937 (1972-02-01), Isett
patent: 4823276 (1989-04-01), Hiwatashi
patent: 4903214 (1990-02-01), Hiwatashi
patent: 4910680 (1990-03-01), Hiwatashi
patent: 5124273 (1992-06-01), Minami
patent: 5264390 (1993-11-01), Nagase et al.
patent: 5272645 (1993-12-01), Kawakami et al.
patent: 5295082 (1994-03-01), Chang et al.
patent: 5375069 (1994-12-01), Satoh et al.
patent: 5422317 (1995-06-01), Hua et al.
patent: 5500805 (1996-03-01), Lee et al.
patent: 5510999 (1996-04-01), Lee et al.
patent: 5689432 (1997-11-01), Blaauw et al.
Kato Naoki
Miyazaki Yoshiaki
Suzuki Katsuyoshi
Yamada Hiromitsu
Garbowski Leigh Marie
Hitachi , Ltd.
Teska Kevin J.
LandOfFree
Method of wiring semiconductor integrated circuit and semiconduc does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of wiring semiconductor integrated circuit and semiconduc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of wiring semiconductor integrated circuit and semiconduc will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2067843