Multiplex communications – Wide area network – Packet switching
Patent
1997-01-09
1999-10-19
Auve, Glenn A.
Multiplex communications
Wide area network
Packet switching
395728, 395729, 395472, 370 851, 370 941, G06F 1314
Patent
active
059702532
ABSTRACT:
A method and apparatus for setting a priority sequence among a plurality of requesters using a common destination within a computer system. An advantage is that all requesters contending for the common destination will have timely access with respect to all other competing requesters. In a first exemplary embodiment of the present invention, a priority controller can use a two-level priority scheme to select the next requester. The first level of priority alternates between an external requester and an on-card requester where every other set of data is from the external requester. The second level of priority alternates between on-card modules during an on-card priority cycle. In an alternative exemplary embodiment, the priority controller can stack a request to transfer acknowledge and data information from an external requester if it is busy. The priority controller also prevents sending an acknowledgment/data cycle out to an external source to prevent sending more data than the FIFO stacks can accommodate. The data may also consist only of acknowledgements.
REFERENCES:
patent: 3641505 (1972-02-01), Artz et al.
patent: 3812469 (1974-05-01), Hauck et al.
patent: 3872447 (1975-03-01), Tessera et al.
patent: 3921150 (1975-11-01), Scheuneman
patent: 3925766 (1975-12-01), Bardotti et al.
patent: 4056844 (1977-11-01), Izumi
patent: 4070704 (1978-01-01), Calle et al.
patent: 4070706 (1978-01-01), Scheuneman
patent: 4130865 (1978-12-01), Heart et al.
patent: 4245306 (1981-01-01), Besemer et al.
patent: 4309754 (1982-01-01), Dinwiddle, Jr.
patent: 4349871 (1982-09-01), Lary
patent: 4400771 (1983-08-01), Suzuki et al.
patent: 4426681 (1984-01-01), Bacot et al.
patent: 4437157 (1984-03-01), Witalka et al.
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4481572 (1984-11-01), Ochsner
patent: 4525777 (1985-06-01), Webster et al.
patent: 4595911 (1986-06-01), Kregness et al.
patent: 4598362 (1986-07-01), Kinjo et al.
patent: 4667288 (1987-05-01), Keeley et al.
patent: 4716527 (1987-12-01), Graciotti
patent: 4722072 (1988-01-01), Price
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4761755 (1988-08-01), Ardini, Jr. et al.
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4807110 (1989-02-01), Pomerene et al.
patent: 4807183 (1989-02-01), Kung et al.
patent: 4829467 (1989-05-01), Ogata
patent: 4843541 (1989-06-01), Bean et al.
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 4860192 (1989-08-01), Sachs et al.
patent: 4860198 (1989-08-01), Takenaka
patent: 4868818 (1989-09-01), Madan et al.
patent: 4878166 (1989-10-01), Johnson et al.
patent: 4888771 (1989-12-01), Benignus et al.
patent: 4891810 (1990-01-01), de Corlieu et al.
patent: 4933901 (1990-06-01), Tai et al.
patent: 4956820 (1990-09-01), Hashimoto
patent: 4959782 (1990-09-01), Tulpule et al.
patent: 4979107 (1990-12-01), Advani et al.
patent: 4992930 (1991-02-01), Gilfeather et al.
patent: 4995035 (1991-02-01), Cole et al.
patent: 5014197 (1991-05-01), Wolf
patent: 5023776 (1991-06-01), Gregor
patent: 5025365 (1991-06-01), Mathur et al.
patent: 5025366 (1991-06-01), Baror
patent: 5043981 (1991-08-01), Firoozmand et al.
patent: 5051946 (1991-09-01), Cubranich et al.
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5068782 (1991-11-01), Scheuneman et al.
patent: 5084871 (1992-01-01), Carn et al.
patent: 5113522 (1992-05-01), Dinwiddie, Jr. et al.
patent: 5115507 (1992-05-01), Callemyn
patent: 5125081 (1992-06-01), Chiba
patent: 5129077 (1992-07-01), Hillis
patent: 5140682 (1992-08-01), Okura et al.
patent: 5148533 (1992-09-01), Joyce et al.
patent: 5165018 (1992-11-01), Simor
patent: 5168570 (1992-12-01), Eckert et al.
patent: 5170472 (1992-12-01), Cwiakala et al.
patent: 5175824 (1992-12-01), Soderbery et al.
patent: 5179705 (1993-01-01), Kent
patent: 5193163 (1993-03-01), Sanders et al.
patent: 5195185 (1993-03-01), Marenin
patent: 5202966 (1993-04-01), Woodson
patent: 5218688 (1993-06-01), Nishida
patent: 5255374 (1993-10-01), Aldereguia et al.
patent: 5255375 (1993-10-01), Crook et al.
patent: 5255378 (1993-10-01), Crawford et al.
patent: 5265257 (1993-11-01), Simcoe et al.
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5303382 (1994-04-01), Buch et al.
patent: 5313602 (1994-05-01), Nakamura
patent: 5367654 (1994-11-01), Furakawa et al.
patent: 5375220 (1994-12-01), Ishikawa
patent: 5388227 (1995-02-01), McFarland
patent: 5444847 (1995-08-01), Iitsuka
patent: 5452239 (1995-09-01), Dai et al.
patent: 5471592 (1995-11-01), Gove et al.
patent: 5559969 (1996-09-01), Jennings
patent: 5603005 (1997-02-01), Bauman et al.
patent: 5623672 (1997-04-01), Popat
patent: 5630077 (1997-05-01), Krein et al.
patent: 5634060 (1997-05-01), Jennings
patent: 5649206 (1997-07-01), Allen
patent: 5659707 (1997-08-01), Wang et al.
Wilson, Jr., "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors", IEEE, 1987.
Auve Glenn A.
Jean Frantz Blanchard
Johnson Charles A.
Starr Mark T.
Unisys Corporation
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