Apparatus and method for a variable step address generator

Details Apparatus and method for a variable step address generator Apparatus and method for a variable step address generator

1996-11-25

1998-04-21

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057426147

ABSTRACT:
A semiconductor random access memory having a complex topology is provided with ROM unit storing every potential row data pattern to be entered in the storage cell array during a test procedure, a variable step address generator, a comparator mechanism, and a control unit. In response to signals from the control unit, the variable step address generator enters each row data pattern at appropriate addresses determined by the periodicity of the complex topography. The variable step address generator is then used to retrieve stored data groups from addresses used to store each ROM data pattern. The retrieved data groups are compared with the ROM data pattern used as a template for the stored data group. A record of the comparison errors can be stored in an erasable memory unit.

REFERENCES:
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5615156 (1997-03-01), Yoshida et al.

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