Memory array of integrated circuits capable of replacing faulty

Details Memory array of integrated circuits capable of replacing faulty Memory array of integrated circuits capable of replacing faulty

1993-04-27

1998-04-21

Beausoliel, Jr., Robert W

Excavating

G06F 1120

Patent

active

057426139

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

This invention relates to a random access data storage system which comprises a plurality of elements, typically integrated circuits or semiconductor chips, each such element comprising an array of memory locations some of which may be faulty.
All memory chips suffer from defects or faults caused by their manufacturing process. Most of these faults are benign in that they do not impair the majority of the memory locations on the chip. Techniques have been developed that repair the defective locations by providing spare locations on the same chip, making the chip appear perfect. Such a chip is called a perfect chip, whereas a chip that contains a small number of faults, but otherwise operates with the same electrical or reliability characteristics as a perfect chip, is called a majority memory chip. Various techniques for tolerating faults within chips are discussed in the prior art introduction of our copending PCT patent application PCT/GB90/01051.
The majority memory chip can take many forms, typically Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Programmable Read Only Memory (PROM). Despite some of their names these are all random access memories (RAMs). Such memory chips are arranged as X bits wide by Y address locations deep. A majority RAM contains some X bits that cannot be read from or written to at some Y addresses.
Our copending PCT patent application PCT/GB90/01051 describes two typical embodiments of a fault tolerant data storage system that can retrieve data in either blocks of multiple bits or single bits. The two embodiments are applicable to any size or shape of array of memory chips. Furthermore any type of majority RAM can be used in the array. However the two embodiments are at their most optimum with a wide array of chips where each majority RAM is defined as a 1 bit by Y address memory. For example an array of 64 chips organised as 4 rows of 16 chips each would require 21 spare chips as envisaged in the second embodiment of PCT/GB90/01051. Using that architecture for an array of 32 rows of 2 chips each would require 35 spare chips.


SUMMARY OF THE INVENTION

In accordance with this invention there is provided a fault tolerant random access data storage system which comprises a plurality of main elements, each element comprising an array of memory locations, a first spare element and a second spare element, each spare element comprising an array of memory locations, means for addressing the elements with the logical addresses of the rows within the arrays being skewed relative to their physical addresses but in a different manner for the different elements, and with the logical addresses of the columns within the arrays being skewed relative to their physical addresses but in a different manner for the different elements, and means for recording faulty memory locations so that if a selected row in a selected main element includes a fault, then a replacement row in the first spare element is selected instead, and if a selected column in a selected main element includes a fault, then a replacement column in the second spare element is selected instead.
The main and spare memory elements may comprise individual integrated circuits (or chips), or some or all of the elements may be combined on a single chip.
In an embodiment of the present invention to be described herein, each of the memory elements comprises a row of two chips, each chip being typically 4 or 8 bits wide and Y addresses deep. With each row consisting of two chips, the overhead (in terms of spare chips) comprises only four spare chips. Also, in contrast to the system of PCT/GB90/01051 which requires additional chips for each new row added to the array of chips, the present invention requires a fixed number of spare chips independent of the number of chips in the array.
Even for the two embodiments of PCT/GB90/01051 there is a significant cost saving over arrays constructed from perfect chips since majority RAMs are available at a significant discount. However it i

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