Semiconductor memory device with row access in selected column b

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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36523003, G11C 800

Patent

active

059700190

ABSTRACT:
A semiconductor memory device which employs a hierarchical word-decode scheme for word selection includes sub-word lines provided for each of column blocks, a control circuit selecting one of the column blocks corresponding to a currently accessed column address in a first case where a currently accessed row address is different from a successively accessed row address, and selecting all of the column blocks in a second case where the currently accessed row address is the same as the successively accessed row address, and a sub-word decoder selectively activating the sub-word lines with respect to all of one or more column blocks selected by the control circuit.

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patent: 5848006 (1998-12-01), Nagata

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