Method and apparatus for modulus error checking

Details Method and apparatus for modulus error checking Method and apparatus for modulus error checking

1996-05-21

1998-04-21

Mai, Tan V.

Boots, shoes, and leggings

G06F 1100

Patent

active

057425337

ABSTRACT:
Apparatus and method for checking the final result of a computer implemented floating point arithmetic unit employs an effective subtract signal, which is already in use and logically required to generate the final result, to select either the requested floating point mathematical combination of modulus 3 operand residue or the compliment of requested mathematical combination of modulus 3 residue of the operands for comparison to the residue of the final result to detect an error in the final result without maintaining the sign value of the individual operand residues or the sign of the resultant residue.

REFERENCES:
patent: 3436647 (1969-04-01), Gobeli et al.
patent: 3887820 (1975-06-01), Glennon
patent: 4338658 (1982-07-01), Toy
patent: 4845659 (1989-07-01), Hrusecky
patent: 4849923 (1989-07-01), Samudrala et al.
patent: 4852039 (1989-07-01), Maheshwari et al.
patent: 4858165 (1989-08-01), Gronowski et al.
patent: 4874961 (1989-10-01), Henderson
patent: 5289396 (1994-02-01), Taniguchi
patent: 5317527 (1994-05-01), Britton et al.
patent: 5321644 (1994-06-01), Schibinger
patent: 5325520 (1994-06-01), Nguyen et al.
patent: 5373461 (1994-12-01), Bearden et al.
patent: 5384723 (1995-01-01), Karim et al.
patent: 5408651 (1995-04-01), Flocken et al.
patent: 5504697 (1996-04-01), Ishida
IBM TDB vol. 32, No. 3a, Aug. 1989, pp. 330-333, Title-Very High-Speed Algorithm for Drawing Conics by Schwartz.
IBM TDB vol. 35, No. 4A, Sep. 1992, pp. 135-136, Title-Early Exception Detection on Store With Convert by Beacom, Handlogten, Levenstein and Patel.
VDHL: Hardware Description and Design by Lipsett, Schaefer, Ussery-Intermetrics Inc. Published by Kluwer Academic Publishers 1989 Index, Chpt. 2,Chpt,5,Chpt.6.
IBM TDB vol. 32, No. 3A, Aug. 1989, pp. 330-333, Title-Enhanced High-Speed Algorithm For Drawing Curves by Schwartz.
IBM TDB vol. 7, No. 11, Apr. 1965, pp. 1042-1045, Title-Modulo-10 and Modulo 11 Self-Check Logic by Greene and Lettieri.
IBM TDB vol. 28, No. 7, Dec. 1985, pp. 2928-2934, Title-System Architecture for Efficient Pipeline Execution . . . by Kriz.
IBM TDB vol. 30, No. 10, Mar. 1988, pp. 303-305, Title-Variable Random Double Bit Error-Injecting Test Module by Garcia, Turner, Wong.
IBM TDB vol. 31, No. 7, Dec. 1988, pp. 149-153, Title-Software Verification of Microcode Transfer Using . . . by Prill, Mandalia.
IBM TDB vol. 31, No. 12, May 1989, pp. 252-257, Title Self-Aligning Robot Gripper by Barenboim.

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