Nonvolatile memory array with NAND string memory cell groups sel

Details Nonvolatile memory array with NAND string memory cell groups sel Nonvolatile memory array with NAND string memory cell groups sel

1998-01-29

1999-10-19

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518517, 36518526, G11C 1606

Patent

active

059699906

ABSTRACT:
A semiconductor nonvolatile memory device where a main bit line is divided into a plurality of sub bit lines via operational connecting means, memory transistors connected to the sub bit lines are arranged in the form of a matrix, and control gate electrodes of these memory transistors are connected to word lines, provided with a means for setting sub bit lines at a programming prohibit potential at the time of a data programming operation; a means for causing a discharge in a selected sub bit line among the sub bit lines set to the programming prohibit potential and placing the non-selected sub bit lines among the sub bit lines in a floating state; and a means for supplying a program voltage to the selected word line.

REFERENCES:
patent: 5524094 (1996-06-01), Nobukata et al.
patent: 5690347 (1997-11-01), Takeuchi et al.
patent: 5715194 (1998-02-01), Hu
patent: 5745413 (1998-04-01), Iwahashi

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