Dual redundant bus interface circuit architecture

Details Dual redundant bus interface circuit architecture Dual redundant bus interface circuit architecture

1984-07-30

1987-09-22

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1340

Patent

active

046959521

ABSTRACT:
An asynchronous bus interface circuit manages the transfer of messages between a host processor memory, and one of two redundant serial data buses by separately processing command words thereby permitting efficient handling of status and data words.

REFERENCES:
patent: 4001783 (1977-01-01), Monahan et al.
patent: 4409656 (1983-10-01), Andersen et al.
patent: 4486826 (1984-12-01), Wolff et al.
patent: 4490785 (1984-12-01), Strecker et al.

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