Virtual address system having fixed common bus cycles

Details Virtual address system having fixed common bus cycles Virtual address system having fixed common bus cycles

1984-02-06

1987-09-22

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1210, G06F 1300

Patent

active

046959475

ABSTRACT:
In an information processing system utilizing a virtual storage, an address translation look-aside buffer for translating a logical address into a physical address is provided to access the main storage by use of the translated physical address. The processing system has a storage control unit for controlling the operation of the address translation look-aside buffer and the main storage, which are connected with a common bus through which addresses and data are transferred on a time-division basis. The storage control unit has a bus control circuit for controlling the common bus so that addresses are transferred from the translation look-aside buffer and data is transferred to the main storage on the common bus at different times.

REFERENCES:
patent: 3693165 (1972-09-01), Reiley
patent: 3761881 (1973-09-01), Anderson
patent: 3764996 (1973-10-01), Ross
patent: 4373179 (1983-02-01), Katsumata
patent: 4449181 (1984-05-01), Young
patent: 4513369 (1985-04-01), Sato
patent: 4520441 (1985-05-01), Bandoh

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