Multiprocessor shared pipeline cache memory with split cycle and

Details Multiprocessor shared pipeline cache memory with split cycle and Multiprocessor shared pipeline cache memory with split cycle and

1984-09-27

1987-09-22

Williams, Jr., Archie E.

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G06F 1300, G11C 700

Patent

active

046959432

ABSTRACT:
A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

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