Monolithically integrated planar semiconductor arrangement

Details Monolithically integrated planar semiconductor arrangement Monolithically integrated planar semiconductor arrangement

1985-08-21

1987-09-22

Edlow, Martin H.

357 53, H01L 2702

Patent

active

046958673

DESCRIPTION:

BRIEF SUMMARY
STATE OF THE ART

The invention is based on a semiconductor arrangement which is designed as a Darlington-transistor-circuit with a drive-transistor and a power transistor, with at least one pn-junction being formed by a substrate having a defined type of conductivity and a zone of an opposite type of conductivity being diffused into the substrate, with a cover electrode disposed over a passivation layer which covers the space charging areas being generated in the reverse bias made and which is connected with the tap of a voltage divider which is diffused as a resistor strip at a distance from the pn-junction, with a blocking strip which is diffused into the substrate between the resistor strip and the pn-junction and which is connected with an outer guard ring delimiting the boundary of the semiconductor arrangement. A semiconductor arrangement known from the U.S. Pat. No. 4,618,875 is designed as a Darlington-transistor-conduit, wherein the two transistors are monolithically integrated in a common substrate in accordance with the planar technique. Thereby, the substrate forms the two collector zones of the two transistors. A passivation layer consisting of silicon dioxide is present on the main surface of the substrate, since this layer covers the main surface with the exception of contact windows. The base-collector-transistions of the two transistors are protected by a metal electrode which is above the passivation layer and which can be called a cover electrode. This semiconductor circuit is also provided with an integrated voltge divider, whose pick off is connected with the cover electrode. The electrostatic field which is emitted from the cover electrode influences the break down voltage on the lower disposed base-collector-transitions which are designed as pn-junctions. By a suitable selection of the voltage divider an adjustment of the break down voltage can be performed, which, however, in the known semi-conductor arrangement can be undesirably influenced due to the inverse current. If the inverse current does flow not only within the base but also into the resistor strip, it may result in a staggering or mismatch of the voltage divider and thereby in a severe dependency of the break down voltage on the inverse current. If the arrangement is used for clamping the emitter-collector inverse voltage in that the inverse current controls the base of the transistor the mismatch of the voltage divider finally results in a strong dependency of the clamping voltage on the collector current, since the base current required for controlling is the result of the collector current and the amplification.


ADVANTAGES OF THE INVENTION

In contrast thereto, the semiconductor arrangement in accordance with the invention is advantageous in that a surface rupture in the area of the resistor strip is prevented due to the different thickness of the passivation layer, since the oxide layer in the area of the resistor strip is designed thicker than in the area of the space charge zone which is adjacent to the pn-junction. The inventive semiconductor arrangement may be a Zener diode, a single transistor of a Darlington-circuit. A thinner part of the passivation layer in the area between the blocking strip and the base area of the power transistor of a Darlington-transistor-circuit results in that the inverse current of the surface rupture flows exclusively into the base of the power transistor. The difference thickness of the passivation layer must be selected according to the given requirements, in particular in dependency on the given embodiment of the circuit and the desired clamping voltage. With a Darlington-transistor-circuit which is used for a control circuit for ignition coils for motor vehicles a 0.5-1 um thinner passivation layer is provided in the area between the blocking strip or stop ring and the base zone of the power transistor than in the remainder areas, for example, with a clamping voltage of 400 Volt.
Advantageous further embodiments are disclosed in the remaining subclaims.


DRAWING

The invention

REFERENCES:
patent: 3395290 (1968-07-01), Farina et al.
patent: 4564771 (1986-01-01), Flohrs
patent: 4599638 (1986-07-01), Flohrs
patent: 4618875 (1986-10-01), Flohrs

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