Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-11-26
2000-10-31
Nguyen, Tan T.
Static information storage and retrieval
Floating gate
Particular biasing
36518512, 36518517, G11C 1600
Patent
active
061412546
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a method for programming a Flash-EPROM type memory.
In this type of memory, each information storage element or memory cell consists of a floating-gate MOS transistor that may be in two states. Thus, in the case of an N channel MOS transistor, in a first state called an erased state, no negative charge, or even a positive charge, is trapped at the floating gate. A conduction channel can then exist between the source and drain of this transistor. In a second state called a programmed state, electrons are trapped at the floating gate. They therefore prevent the creation of a conduction channel in the substrate between the source and drain. In this case, the transistor is off and behaves like an open circuit.
In a Flash-EPROM type memory, the passage of an electron from the conduction channel to the floating gate is done by a so-called hot electron method. To this end, high voltages are applied between the control gate and the drain of this same floating-gate transistor while the source is connected to the ground. These voltages enable the passage of very high-energy electrons (hot electrons), coming from the channel thus created, to the floating gate. The electrons are then trapped in the floating gate and constitute an information element. The removal of the charges, or erasure, is prompted by a tunnel effect.
A memory array consists of words comprising, in one example, at least eight cells each capable of containing a binary information element (namely one of the two previous states). FIG. 1 shows a partial view of an architecture of this kind. These cells may be selected individually. They are arranged in rows and columns.
In a standard architecture, all the floating-gate transistors of the memory cells of one and the same word, in other words in a same byte, have their control gate connected to one and the same voltage source by a word line and their source connected to one and the same main electrode of a selection transistor by a connection. This selection transistor permits or does not permit the biasing of the source of the floating-gate transistors of the word. An architecture of this kind with a selection transistor of this kind is described in the patent application EP-A-0 704 851, conform with the preamble to claim 1. The utility of the selection transistor is that it prevents the depletion of the floating-gate transistor of a cell and thus provides perfect uniformity of the threshold voltage of the cells that are the object of an erasure.
This same selection transistor has its other main electrode, namely its drain or source electrode, connected to a source vertical connection of words that are vertically adjacent. The vertically adjacent words are therefore on different rows. This selection transistor enables the biasing or non-biasing of the common sources of the floating-gate transistors of one and the same word. These words have Q bytes. If Q=1, the word has one byte. The control gates of the floating-gate transistors of the cells of the words of one and the same row are connected to one and the same word line. Furthermore, the control gates of the selection transistors of the words of one and the same row are connected to one and the same word selection line receiving an associated selection signal that is often identical to the signal applied to the word line.
With an architecture of this kind, there are constraints that limit programming of several memory cells of one and the same word during one and the same programming cycle. Indeed, during the programming operation, the control gate of each cell of one and the same row is subjected to a high voltage. The drain of the floating-gate transistor of a cell that is selected to be programmed is taken to a high voltage that is high enough to accelerate charges in a channel. The source of this floating-gate transistor is connected to the ground. This high voltage enables charges to acquire high energy, and produces a high current through this channel (500 .mu.A/cell). Thus for one byte, the current produced duri
REFERENCES:
patent: 5615147 (1997-03-01), Chang et al.
patent: 5717636 (1998-02-01), Dallabora et al.
patent: 5978265 (1999-11-01), Kirisawa et al.
patent: 5991199 (1999-11-01), Brigati et al.
Brigati Alessandro
Devin Jean
Leconte Bruno
Bongini Stephen C.
Galanthay Theodore E.
Nguyen Tan T.
STMicroelectronics S.A.
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