Semiconductor wafer with interconnect between dies for testing a

Details Semiconductor wafer with interconnect between dies for testing a Semiconductor wafer with interconnect between dies for testing a

Filed on

1996-10-31

Date issued

1999-10-19

Examiner

Ballato, Josie

Patent Class

Electricity: measuring and testing

SubClass

Fault detecting in electric circuits and of electric components

SubSubClass

Of individual circuit component or element

Other Related Categories

371 225, G01R 3102

Type

Patent

Status

active

Patent number

059695382

Description

ABSTRACT:
Integrated circuit die on a wafer are tested individually, without probing any of the die, using die resident circuitry and connections to selectively provide either a bypass mode wherein the die has direct pad-to-pad connectivity or a functional mode wherein the die has pad to functional core logic connectivity. The die framework further provides a fault tolerant circuit to select a die on a wafer to be placed in functional mode while other die remain in bypass mode.

REFERENCES:
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patent: 5286656 (1994-02-01), Keown et al.
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patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 5389556 (1995-02-01), Rostoker et al.
patent: 5389873 (1995-02-01), Ishii et al.
patent: 5391984 (1995-02-01), Worley
patent: 5568492 (1996-10-01), Flint et al.

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