Semiconductor device comprising a plurality of interconnection p

Details Semiconductor device comprising a plurality of interconnection p Semiconductor device comprising a plurality of interconnection p

1997-06-24

1999-10-19

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257204, 257206, 257207, 257208, 257211, 257750, 257758, 257763, H01L 2348

Patent

active

059694203

ABSTRACT:
On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

REFERENCES:
patent: 5060045 (1991-10-01), Owada et al.
patent: 5119169 (1992-06-01), Kozono et al.
"Switched-Source-Impedance CMOS Circuit For Low Standby Subthreshold Current Giga-Scale LSI's", Horiguchi et al., 1993 Symposium on VLSI Circuit Dig. of tech Papers. pp. 47-48.
"Standby/Active Mode Logic for Sub-1 V 1G/4Gb DRAMs", Takashima et al., 1993 Symposium on VLSI Circuit Dig. of Tech Papers. pp. 83-84.
"A 34NS 16MB DRAM With Controllable Voltage Down Concertor", Arimoto et al., ESSCIRS Proceedings Sep. 1991, pp. 21-24.

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