Field-effect compound semiconductive transistor with GaAs gate t

Details Field-effect compound semiconductive transistor with GaAs gate t Field-effect compound semiconductive transistor with GaAs gate t

1990-02-20

1992-11-03

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

257194, H01L 2980

Patent

active

051612356

ABSTRACT:
Multi-layer heterostructure transistors, and methods for making them, involve the use of a p+ doped GaAs gate for an n-channel device to increase barrier height and reduce turn-on threshold. A p++-i-p substrate helps to reduce source and drain capacitances and control short-channel effects. Use of one relatively high temperature photoresist in the fabrication process facilitates alignment of ohmic contact depositions with the source and drain regions.

REFERENCES:
patent: 4424525 (1984-01-01), Mimura
patent: 4862228 (1990-08-01), Ralph
patent: 4905059 (1990-02-01), Shur
patent: 4907048 (1990-03-01), Ando
IEEE Transactions on Electron Devices, vol. ED-34, No. 2, Feb. 1987, "Design of Enhanced Schottky-Barrier AlGaAsl GaAs MODFET'S Using Highly Doped pt Surface Layers", by Priddy et al., pp. 175-179.
IEEE Transactions on Electron Devices, vol. ED-36, No. 5, May 1989, "Influence of Quantum Well Width on Device Performance of Al.sub.0.30 Ga.sub.0.70 As/In.sub.0.25 Ga.sub.0.75 As (on GaAs) MODFET's ", by Nguyen et al., pp. 833-838.
IEEE Transactions on Electron Devices, vol. 37, No. 6, Jun., 1990, "High-Performance Self-Aligned p+In GaAs Epitaxial JFET's Incorporating AlGaAs Etch Stop Layer", by Abrokwah et al., pp. 1529-1531.

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