Memory controller for using reserved DRAM addresses for EMS

Details Memory controller for using reserved DRAM addresses for EMS Memory controller for using reserved DRAM addresses for EMS

1990-11-13

1992-11-03

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 36424531, 36523001, 36523002, 36523006, G06F 1200, G06F 1210, G11C 800

Patent

active

051612186

ABSTRACT:
A memory controller which can map EMS addresses into the DRAM behind video RAM addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.

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