Temporary pipeline register file for a superpipelined superscala

Details Temporary pipeline register file for a superpipelined superscala Temporary pipeline register file for a superpipelined superscala

1993-11-17

2000-10-03

Myers, Paul R.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

G06F 1500

Patent

active

061287210

ABSTRACT:
A processor method and apparatus. The processor has an execution pipeline, a register file and a controller. The execution pipeline is for executing an instruction and has a first stage for generating a first result and a last stage for generating a final result. The register file is for storing the first result and the final result. The controller makes the first result stored in the register file available in the event that the first result is needed for the execution of a subsequent instruction. By storing the result of the first stage in the register file, the length of the execution pipeline is reduced from that of the prior art. Furthermore, logic required for providing inputs to the execution pipeline is greatly simplified over that required by the prior art.

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European Search Report dated Mar. 1, 1995; Examiner T. Daskalakis.

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