Circuit and method of detecting an invalid clock signal

Details Circuit and method of detecting an invalid clock signal Circuit and method of detecting an invalid clock signal

1991-05-28

1992-11-03

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

377 28, 328120, H03K 519

Patent

active

051611759

ABSTRACT:
A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

REFERENCES:
patent: 3898444 (1975-08-01), Cordi et al.
patent: 4345209 (1982-08-01), Walker
patent: 4553426 (1985-11-01), Cepurka
patent: 4628269 (1986-12-01), Hunninghaus et al.

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