Field-programmable redundancy apparatus for memory arrays

Details Field-programmable redundancy apparatus for memory arrays Field-programmable redundancy apparatus for memory arrays

1991-11-27

1992-11-03

Beausoliel, Robert W.

Excavating

371 111, G06F 1120

Patent

active

051611570

ABSTRACT:
A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

REFERENCES:
patent: 4263664 (1981-04-01), Owen et al.
patent: 4274012 (1981-06-01), Simko
patent: 4300212 (1981-11-01), Simko
patent: 4326134 (1982-04-01), Owen et al.
patent: 4393474 (1983-07-01), McElroy
patent: 4404475 (1983-09-01), Drori et al.
patent: 4581739 (1986-04-01), McMahon, Jr.
patent: 4598388 (1986-07-01), Anderson
patent: 4599706 (1986-07-01), Guterman
patent: 4617652 (1986-10-01), Simko
patent: 4745582 (1988-05-01), Fukushi et al.
patent: 4750158 (1988-06-01), Giebel et al.
patent: 4768169 (1988-10-01), Perlegos
patent: 4791615 (1988-12-01), Pelly, III et al.
patent: 4827452 (1989-05-01), Tayama et al.
patent: 4849938 (1989-07-01), Furutani et al.
patent: 4862416 (1989-08-01), Takeuchi
patent: 4975881 (1990-12-01), Kagami
patent: 4980859 (1990-12-01), Guterman et al.
Wey, et al., "On the Design of a Redundant Programmable Logic Array (RPLA)," IEEE Journal of Solid-State Circuits, vol. Sc-22, No. 1, Feb. 1987.
"JEDEC Standard No. 21-B: Configuration for Solid State Memories", Electronics Industries Association, Washington D.C., Dec. 1988.

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