VLIW processor which processes compressed instruction format

Details VLIW processor which processes compressed instruction format VLIW processor which processes compressed instruction format

1996-05-15

1998-12-22

Coleman, Eric

395391, G06F 938

Patent

active

058527419

ABSTRACT:
A VLIW processor uses a compressed instruction format that allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

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