Excavating
Patent
1997-09-08
1998-12-22
Canney, Vincent P.
Excavating
G06F 1100
Patent
active
058526188
DESCRIPTION:
BRIEF SUMMARY
This application is a 371 of PCT/JP 76/00031 of Dec. 1, 1996.
1. Technical Field
This invention relates to a test pattern generator for testing semiconductor devices, and more particularly to a test pattern generator for testing multi-bit high speed semiconductor memory devices.
2. Background Art
An example of a conventional semiconductor test system for evaluating the quality of semiconductor devices under test is shown in FIG. 5. In the example of FIG. 5, the device under test is a memory. As shown in the drawing, an address signal is provided from an address generator 2 to the memory device under test, and a data signal is provided from a data generator 3 to the memory device under test. These data signals are arranged corresponding to the pin arrangement or the like of the memory device under test by a data selector 4, and are given to the memory device 5 under test. After writing the data in the memory device 5, in the read step, the read out data is given to a logic comparator 6. At the same time, a data signal generated by the data generator 3 is provided to the logic comparator as expected value data through the data selector 4. Each of the generators described above is controlled by a sequence controller 1. A pattern generator is comprised of these generators and the sequence controller in the foregoing.
FIG. 6 shows an example of structure of the conventional data generator 3. As shown in FIG. 6, various arithmetic operations are performed by a data operator 30 for the data provided to an arithmetic unit 32 from an instruction memory 31. The result of the arithmetic operation is again given to the arithmetic unit 32 through a register 33, and an arithmetic operation such as an add/subtract operation or a shift operation is performed. The output of the arithmetic unit 32 is supplied to an exclusive OR gate 35. The exclusive OR gate 35 is controlled by an output signal of a flag register 34. When the output signal of the flag register shows "1", the data from the arithmetic unit is inverted by the exclusive OR gate. The data signal from the exclusive OR gate 35 is provided to the data selector 4.
As described above, in general, the data signal output from the data generator 3 is comprised of a multi-bit data width, typically 18 bits or 36 bits of data width at present. This is because the bit number of the data generator has been increased in response to the increase in the data width of a memory under test (hereafter referred to as "MUT").
However, if the number of bits of the data generator has to be increased in the same manner such as to 72 bits or 144 bits in response to the data width and also has to meet the increasing speed of MUT, the size and speed of the hardware in the data operator 30 must be increased accordingly. That is, the scale of the hardware for an arithmetic unit, registers and their peripheral circuits will be dramatically increased. In addition, the size of the pattern generator will be too large and the cost will be too high.
In order to realize an arithmetic unit to match the multi-bit and high speed data, it is a common practice to employ a bit slice structure by dividing the data into groups of several bits, and processing the divided data in a pipeline structure having multiple of register stages. However, in such a case, if the data bit width is increased by two times, the corresponding size of the hardware is not simply increased by two times but more than the two times, i.e., further increased by several times more.
In recent years, the data width and operation speed of cache memories used, for example, for a processor in a high speed computer are increasing. It is predicted that the bit width of 36 or 72, and even 144 sill be realized in the near future. For testing such high speed and multi-bit memories, it is necessary to use a high speed test system. If the pattern generator with high speed and multi-bit data is to be formed in the same manner in the conventional technology, it will result in significant increase in the size and the cost of the test system.
There
REFERENCES:
patent: 5488614 (1996-01-01), Shima
patent: 5617426 (1997-04-01), Koenemann et al.
Advantest Corp.
Canney Vincent P.
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