Charge redistribution analog-to-digital converter with system ca

Details Charge redistribution analog-to-digital converter with system ca Charge redistribution analog-to-digital converter with system ca

1995-06-07

1998-12-22

Young, Brian K.

Coded data generation or conversion

Converter calibration or testing

341155, 341172, H03M 110

Patent

active

058524150

ABSTRACT:
A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.

REFERENCES:
patent: 3286232 (1966-11-01), Stanford
patent: 3988689 (1976-10-01), Ochi et al.
patent: 4077035 (1978-02-01), Yee
patent: 4129863 (1978-12-01), Grav et al.
patent: 4143361 (1979-03-01), Tammes et al.
patent: 4144527 (1979-03-01), Butler et al.
patent: 4180807 (1979-12-01), Eichelberger et al.
patent: 4190854 (1980-02-01), Redfern
patent: 4191900 (1980-03-01), Redfern et al.
patent: 4222107 (1980-09-01), Mrozowski et al.
patent: 4250494 (1981-02-01), Butler et al.
patent: 4272760 (1981-06-01), Prazak et al.
patent: 4295089 (1981-10-01), Cooperman
patent: 4348658 (1982-09-01), Carter
patent: 4399426 (1983-08-01), Tan
patent: 4429282 (1984-01-01), Saari
patent: 4439693 (1984-03-01), Lucas et al.
patent: 4458237 (1984-07-01), Domogalla
patent: 4517549 (1985-05-01), Tsukakoshi
patent: 4542354 (1985-09-01), Robinton et al.
patent: 4543953 (1985-10-01), Slocum et al.
patent: 4553052 (1985-11-01), Takahashi
patent: 4555668 (1985-11-01), Gregorian et al.
patent: 4563654 (1986-01-01), Arai et al.
patent: 4577228 (1986-03-01), Arai et al.
patent: 4620179 (1986-10-01), Cooper et al.
patent: 4654815 (1987-03-01), Marin et al.
patent: 4677422 (1987-06-01), Naito
patent: 4700174 (1987-10-01), Sutherland et al.
patent: 4709225 (1987-11-01), Welland et al.
patent: 4777451 (1988-10-01), Tohyama
patent: 4803462 (1989-02-01), Hester et al.
patent: 4804960 (1989-02-01), Fernandes et al.
patent: 4812817 (1989-03-01), Bernard
patent: 4829266 (1989-05-01), Pernici et al.
patent: 4831381 (1989-05-01), Hester
patent: 4833418 (1989-05-01), Quintus et al.
patent: 4881044 (1989-11-01), Kinoshita et al.
patent: 4883987 (1989-11-01), Fattaruso
patent: 4907002 (1990-03-01), Kawada
patent: 4982194 (1991-01-01), Bacrania et al.
patent: 5006853 (1991-04-01), Kiriaki et al.
patent: 5014055 (1991-05-01), Dingwall et al.
patent: 5016014 (1991-05-01), Bitting
patent: 5036322 (1991-07-01), Barrow et al.
patent: 5043732 (1991-08-01), Robertson et al.
patent: 5047665 (1991-09-01), Burt
patent: 5077489 (1991-12-01), Gola et al.
patent: 5124663 (1992-06-01), McEntarfer et al.
patent: 5138319 (1992-08-01), Tesch
patent: 5184130 (1993-02-01), Mangelsdorf
patent: 5220206 (1993-06-01), Tsang et al.
patent: 5233180 (1993-08-01), Tsuruta et al.
patent: 5235333 (1993-08-01), Naylor et al.
patent: 5245223 (1993-09-01), Lim et al.
patent: 5248974 (1993-09-01), Fattaruso et al.
patent: 5272395 (1993-12-01), Vincelette
patent: 5381148 (1995-01-01), Mueck et al.
patent: B14399426 (1987-07-01), Tan
Akazawa, Y. et al., New Linearity Error Correction Technology for A/D and D.A Converter LSI Japanese Journal of Applied Physics, vol. 22 (1983) Supplement 22-1, pp. 115-119.
Allstot, D. J. et al., "An Electrically-Programmable Switched Capacitor Filter," IEEE J. Solid-State Circuits, vol. SC-14, No. 6, Dec. 1979, pp. 1034-1041.
Allstot, D. J., "A Precision Variable-Supply CMOS Comparator," IEEE Journal Solid-State Circuits, vol. SC-17, No. 6, pp. 1080-1087, Dec. 1982.
Analog Devices, 1992 Data Converter Reference Manual, product #AD682, 4-41 and 4-47 to 4-48.
Analog Devices, Preliminary Technical Data, product #AD7882, Sep. 1993, pp. 1-12.
Beresford. R., "A self-calibrating d-a converter." Electronics, Sep. 22, 1981, p. 144.
Bienstman, L. A. et al., "An 8-Channel 8b .mu.P Compatible NMOS Converter with Programmable Ranges." 1980 IEEE International Solid-State Circuits Conference, pp. 16-17.
Bienstman, L. A. et al., "An Eight-Channel 8 Bit Microprocessor Compatible NMOS D/A Converter with Programmable Scaling," IEEE J. Solid-State Circuits, vol. SC-15, No. 6, Dec. 1980, pp. 1051-1058.
Bon, M. et al., "All-Symbolic Analysis Technique for Multiphase Switched Capacitor Networks." pp. 655-660 (no date given).
Cooperman, M. et al., "Charge Redistribution Codec," J. Solid-State Circuits, vol. SC-16, No. 3, pp. 155-162, Jun. 1981.
Crystal Semiconductor Corporation, "16-Bit, 100 kHz Serial-Output A/D Converter", Preliminary Product Information, DS45PP2, Jan. 1989, pp. B-95-B115.
Dannenberg, R. E., "Closed Loop Digital-to-Analog Conversion," IBM Technical Disclosure Bulletin, vol. 20, No. 6, pp. 2332-2333, Nov. 1977.
De Wit, M. et al., "A Low-Power 12-b Analog-to-Digital Converter with On-Chip Precision Trimming," IEEE J. of Solid-State Circuits, vol. 28, No. 4, Apr. 1993, pp. 455-461.
Dobberstein, E. A., "Auto-Preregulating Coverter with Surge Control," IBM Technical Disclosure Bulletin, vol. 23, No. 8, pp. 3556-3558, Jan. 1981.
Eriksson, S., "Realization of Synchronous Wave Switched-Capacitor Filters," Dept. of Electrical Eng, Linkoping, University, Linkoping, Sweden, pp. 650-654 (no date given).
Fiedler, H. L. et al., "A 5-Bit Building Block for 20 Mhz A/D Converters," IEEE J. Solid-State Circuits, vol. SC-16, No. 3, pp. 151-155 Jun. 1981.
Fotouhi, B. et al., "An NMOS 12b Monotonic 25.mu.s A/D Converter," 1979 IEEE International Solid-State Circuits Conference, pp. 186-187.
Fotouhi, B. et al., "High-Resolution A/D Conversion in MOS/LSI," IEEE J. Solid-State Circuits, vol. SC-14, No. 6, Dec. 1979, pp. 920-926.
Gheewala, T. R., "Parallel, Flux Redistribution D/A and A/D Converters," IBM Technical Disclosure Bulletin, vol. 20, No. 6, pp. 2480-2482, Nov. 1977.
Gillis, M. A. et al., "Supply Tracking Digital-to-Analog Converter," IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978, pp. 4507-4508.
Gregorian, R. et al., "Offset Free High-Resolution D/A Converter," American Microsystems, Inc., Santa Clara, CA, 1980, pp. 316-319.
Gregorian, R., "High-resolution switched-capacitor D/A converter," Microelectronics Journal, vol. 12, No. 2, 1981, pp. 10-13.
Gregorian, R. et al., "An Integrated Single-Chip PCM Voice Codec with Filters," IEEE J. Solid-State Circuits, vol. SC-16, No. 4, Aug. 1981, pp. 322-333.
Hague et al., "Two Chip PCM Voice Codec with Filters," IEEE J. Solid-State Circuits, vol. SC-14, No. 6, Dec. 1979, pp. 963-964.
Hamade, A. R. et al., "A Single-Chip 8-Bit A/D Converter," IEEE J. Solid-State Circuits, Dec. 1976, vol. SC-11, No. 6, pp. 154-155.
Hampel, D. et al., "Application of Monolithic CMOS Switched-Capacitor Filters and Amplifiers for Signal Processing," IEEE Trans. on Communications, vol. COM-28, No. 10, Oct. 1980, pp. 1828-1831.
Herbst, D. et al., "Master-Slice SC Filters," Lehrstuhl Bauelemente der Electrotechnik, University of Dortmund, West Germany, pp. 639-643 (no date given).
Holloway, L., "Elimination of Offset During Analog-to-Digital Conversion," IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977, pp. 3610-3611.
Hornak, T. et al., "A High Precision Component-Tolerant A/D Converter," IEEE J. Solid-State Circuits, vol. SC-10, No. 6, Dec. 1975, p. 386.
Iwata, A. et al., "Low Power PCM CODEC and Filter System," IEEE J. Solid-State Circuits, vol. SC-16, No. 2, Apr. 1981, pp. 73-79.
Kleine, U. et al., "Real-Time Programmable Unit-Element SC Filter for LPC Synthesis," Electronics Letters, Aug. 20, 1981, vol. 17, No. 17, pp. 600-602.
Kurth, C. F. et al., "Two-Port Analysis of Cascaded Swiched-Capacitor Networks," IEEE 1978.
Kurth, C. F., "Two-Port Analysis of SC Networks with Continuous Input Signals," The Bell System Technical Journal, vol. 59, No. 8, Oct. 1980, pp. 1297-1316.
Lee, H.S. et al., "Self-Calibration Technique for A/D Converters," IEEE Trans. on Circuits and Systems, vol. CAS-30, No. 3, Mar. 19

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