Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

1997-02-05

1998-12-22

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257763, 257740, H01L 2348, H01L 2352, H01L 2940

Patent

active

058523286

ABSTRACT:
After forming a first wire on a first interlayer insulation film, a second interlayer insulation film is formed and planarized, to thereby form a via hole. At this stage, the via hole is formed off the first wire. Next, after making an exposed edge and an exposed side wall of the first wire slanted surfaces, a second wire is formed with or without a conductive film buried within the via hole. Since the side wall of the first wire is a slanted surface in this manner, it is possible to completely bury a wire material of the second wire or the conductive film within the via hole, and therefore, it is possible to ensure electric conduction all over the slanted surfaces of the first wire. As a result, even if the via hole which connects the first wire in a lower layer and the second wire in an upper layer is formed of f the first wire, an increase in a wire resistance in the via hole is prevented.

REFERENCES:
patent: 3725743 (1973-04-01), Murayama
patent: 4713682 (1987-12-01), Erie et al.
patent: 4767724 (1988-08-01), Kim et al.
patent: 4860084 (1989-08-01), Shibata
Hiroshi Nishimura, Tatsuya Yamada and Shin-ichi Ogawa, "Reliable Submicron Vias Using Aluminum Alloy High Temperature Sputter Filling," Proceedings, Eighth International IEEE VLSI Multilevel Interconnection Conference, (pp. 170-176), 1991.

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