Patent
1993-09-14
1996-05-21
Downs, Robert W.
G06F 1518
Patent
active
055198139
ABSTRACT:
A neuron unit includes first shift registers for storing first weighting coefficients; second shift registers for storing second weighting coefficients; a first gate circuit for obtaining first logical products of first binary input signals and the first weighting coefficients; a second gate circuit for obtaining second logical products of second binary input signals and the second weighting coefficients; a third gate circuit for obtaining a logical sum of the first logical products, and for outputting a first binary response signal corresponding to the logical sum; a fourth gate circuit for obtaining a logical sum of the second logical products, and for outputting a second binary response signal corresponding to the logical sum; a signal generator for outputting a binary signal; and an output circuit for outputting a binary output signal, the first binary response signal being used as the binary output signal when values of the first and second binary response signals differ from each other, and the binary signal output from the signal generator being used as the binary output signal when values of the first and second binary response signals are equal to each other.
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Eguchi Hirotoshi
Furuta Toshiyuki
Downs Robert W.
Ricoh & Company, Ltd.
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