Pipelined hardware implementation of a hashing algorithm

Details Pipelined hardware implementation of a hashing algorithm Pipelined hardware implementation of a hashing algorithm

1998-02-12

2000-07-18

Swann, Tod R.

Cryptography

Particular algorithmic function encoding

Public key

380 28, H04L 900, H04L 930

Patent

active

060918217

ABSTRACT:
A hardware implementation of a hashing algorithm is presented. In a first pipeline stage, a first memory stores input data for the hashing algorithm. Data is selected out of the first memory, for example, using a counter which is reset and incremented by differing values depending upon the round of the algorithm. A second memory stores constants used for the hashing algorithm. Constants are selected out of the second memory, for example, using a counter. An adder adds data from the first memory and a constant from the second memory with a state value selected, for example, using a multiplexer. The result is stored as an intermediate algorithm value in a first pipeline register. In a second pipeline stage a second adder adds one of a plurality of hashing function values to the intermediate algorithm value in the first pipeline register. The result is shifted. A third adder adds the shifted result to one of the plurality of state values and places the result into a second pipeline register.

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